`include "define.v"

module IF(
input wire clk,
input wire rst,
input wire [31:0] jaddr,
input wire jce,
output reg [31:0] pc,
output reg romCe
);

always@(*)
if(rst==`Enable) romCe=`Disenable;
else 			 romCe=`Enable;

always@(posedge clk)
if(romCe==`Disenable) pc=`Zero;
else if(jce== `Valid) pc=jaddr;
else pc=pc+4;

endmodule
